STG CRG

The JH-7110 system provides the following STG CRG control registers.

Clock HIFI4 Core

Table 1. Clock HIFI4 Core Register Description
Offset 16’h0
Access RW
Bit Name Default Description
[31] clk_icg 0 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

Clock USB APB

Table 2. Clock USB APB Register Description
Offset 16’h4
Access RW
Bit Name Default Description
[31] clk_icg 0 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

Clock USB UTMI APB

Table 3. Clock USB UTMI APB Register Description
Offset 16’h8
Access RW
Bit Name Default Description
[31] clk_icg 0 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

Clock USB AXI

Table 4. Clock USB AXI Register Description
Offset 16’hc
Access RW
Bit Name Default Description
[31] clk_icg 0 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

Clock USB IPM

Table 5. Clock USB IPM Register Description
Offset 16’h10
Access RW
Bit Name Default Description
[31] clk_icg 0 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] clk_divcfg 24’d2 Clock divider coefficient:
  • Max: 2
  • Default: 2
  • Min: 2
  • Typical: 2

Clock USB STB

Table 6. Clock USB STB Register Description
Offset 16’h14
Access RW
Bit Name Default Description
[31] clk_icg 0 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] clk_divcfg 24’d4 Clock divider coefficient:
  • Max: 4
  • Default: 4
  • Min: 4
  • Typical: 4

Clock USB APP 125

Table 7. Clock USB APP 125 Register Description
Offset 16’h18
Access RW
Bit Name Default Description
[31] clk_icg 0 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

Clock USB Reference Clock

Table 8. Clock USB Reference Clock Register Description
Offset 16’h1c
Access RW
Bit Name Default Description
[31] Reserved 0 Reserved
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] clk_divcfg 24’d2 Clock divider coefficient:
  • Max: 2
  • Default: 2
  • Min: 2
  • Typical: 2

U0 Clock PCIe AXI MST 0

Table 9. U0 Clock PCIe AXI MST 0 Register Description
Offset 16’h20
Access RW
Bit Name Default Description
[31] clk_icg 0 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

U0 Clock PCIe APB

Table 10. U0 Clock PCIe APB Register Description
Offset 16’h24
Access RW
Bit Name Default Description
[31] clk_icg 0 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

U0 Clock PCIe TL

Table 11. U0 Clock PCIe TL Register Description
Offset 16’h28
Access RW
Bit Name Default Description
[31] clk_icg 0 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

U1 Clock PCIe AXI MST 0

Table 12. U1 Clock PCIe AXI MST 0 Register Description
Offset 16’h2c
Access RW
Bit Name Default Description
[31] clk_icg 0 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

U1 Clock PCIe APB

Table 13. U1 Clock PCIe APB Register Description
Offset 16’h30
Access RW
Bit Name Default Description
[31] clk_icg 0 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

U1 Clock PCIe TL

Table 14. U1 Clock PCIe TL Register Description
Offset 16’h34
Access RW
Bit Name Default Description
[31] clk_icg 0 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

Clock PCIe 01 SLV DEC Main

Table 15. Clock PCIe 01 SLV DEC Main Register Description
Offset 16’h38
Access RW
Bit Name Default Description
[31] clk_icg 1 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

Clock Security HCLK

Table 16. Clock Security HCLK Register Description
Offset 16’h3c
Access RW
Bit Name Default Description
[31] clk_icg 0 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

Clock Security Miscellaneous AHB

Table 17. Clock Security Miscellaneous AHB Register Description
Offset 16’h40
Access RW
Bit Name Default Description
[31] clk_icg 0 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

Clock STG MTRX Group 0 Main

Table 18. Clock STG MTRX Group 0 Main Register Description
Offset 16’h44
Access RW
Bit Name Default Description
[31] clk_icg 1 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

Clock STG MTRX Group 0 Bus

Table 19. Clock STG MTRX Group 0 Bus Register Description
Offset 16’h48
Access RW
Bit Name Default Description
[31] clk_icg 1 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

Clock STG MTRX Group 0 STG

Table 20. Clock STG MTRX Group 0 STG Register Description
Offset 16’h4c
Access RW
Bit Name Default Description
[31] clk_icg 1 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

Clock STG MTRX Group 1 Main

Table 21. Clock STG MTRX Group 1 Main Register Description
Offset 16’h50
Access RW
Bit Name Default Description
[31] clk_icg 1 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

Clock STG MTRX Group 1 Bus

Table 22. Clock STG MTRX Group 1 Bus Register Description
Offset 16’h54
Access RW
Bit Name Default Description
[31] clk_icg 1 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

Clock STG MTRX Group 1 STG

Table 23. Clock STG MTRX Group 1 STG Register Description
Offset 16’h58
Access RW
Bit Name Default Description
[31] clk_icg 1 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

Clock STG MTRX Group 1 HIFI

Table 24. Clock STG MTRX Group 1 HIFI Register Description
Offset 16’h5c
Access RW
Bit Name Default Description
[31] clk_icg 1 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

Clock E2 RTC

Table 25. Clock E2 RTC Register Description
Offset 16’h60
Access RW
Bit Name Default Description
[31] clk_icg 0 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] clk_divcfg 24’d24 Clock divider coefficient:
  • Max: 24
  • Default: 24
  • Min: 24
  • Typical: 24

Clock E2 Core

Table 26. Clock E2 Core Register Description
Offset 16’h64
Access RW
Bit Name Default Description
[31] clk_icg 1 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

Clock E2 DBG

Table 27. Clock E2 DBG Register Description
Offset 16’h68
Access RW
Bit Name Default Description
[31] clk_icg 0 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

Clock DMA AXI

Table 28. Clock DMA AXI Register Description
Offset 16’h6c
Access RW
Bit Name Default Description
[31] clk_icg 0 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

Clock DMA AHB

Table 29. Clock DMA AHB Register Description
Offset 16’h70
Access RW
Bit Name Default Description
[31] clk_icg 0 1: Clock enable / 0: Clock disable
[30] Reserved 0 Reserved
[24:29] Reserved 0 Reserved
[0:23] Reserved 0 Reserved

Software RESET Address Selector

Table 30. Software RESET Address Selector Register Description
Offset 16’h74
Access RW
Bit Name Default Description
[0] rstn_u0_stg_syscon_presetn 0
  • 1: Assert reset
  • 0: De-assert reset
[1] rst_u0_hifi4_rst_core 1
  • 1: Assert reset
  • 0: De-assert reset
[2] rst_u0_hifi4_rst_axi 1
  • 1: Assert reset
  • 0: De-assert reset
[3] rstn_u0_sec_top_hresetn 1
  • 1: Assert reset
  • 0: De-assert reset
[4] rst_u0_e2_sft7110_rst_core 1
  • 1: Assert reset
  • 0: De-assert reset
[5] rstn_u0_dma1p_8ch_56hs_rstn_axi 1
  • 1: Assert reset
  • 0: De-assert reset
[6] rstn_u0_dma1p_8ch_56hs_rstn_ahb 1
  • 1: Assert reset
  • 0: De-assert reset
[7] rstn_u0_cdn_usb_rstn_axi 1
  • 1: Assert reset
  • 0: De-assert reset
[8] rstn_u0_cdn_usb_rstn_usb_apb 1
  • 1: Assert reset
  • 0: De-assert reset
[9] rstn_u0_cdn_usb_rstn_utmi_apb 1
  • 1: Assert reset
  • 0: De-assert reset
[10] rstn_u0_cdn_usb_rstn_pwrup 1
  • 1: Assert reset
  • 0: De-assert reset
[11] rstn_u0_plda_pcie_rstn_axi_mst0 1
  • 1: Assert reset
  • 0: De-assert reset
[12] rstn_u0_plda_pcie_rstn_axi_slv0 1
  • 1: Assert reset
  • 0: De-assert reset
[13] rstn_u0_plda_pcie_rstn_axi_slv 1
  • 1: Assert reset
  • 0: De-assert reset
[14] rstn_u0_plda_pcie_rstn_brg 1
  • 1: Assert reset
  • 0: De-assert reset
[15] rstn_u0_plda_pcie_rstn_pcie 1
  • 1: Assert reset
  • 0: De-assert reset
[16] rstn_u0_plda_pcie_rstn_apb 1
  • 1: Assert reset
  • 0: De-assert reset
[17] rstn_u1_plda_pcie_rstn_axi_mst0 1
  • 1: Assert reset
  • 0: De-assert reset
[18] rstn_u1_plda_pcie_rstn_axi_slv0 1
  • 1: Assert reset
  • 0: De-assert reset
[19] rstn_u1_plda_pcie_rstn_axi_slv 1
  • 1: Assert reset
  • 0: De-assert reset
[20] rstn_u1_plda_pcie_rstn_brg 1
  • 1: Assert reset
  • 0: De-assert reset
[21] rstn_u1_plda_pcie_rstn_pcie 1
  • 1: Assert reset
  • 0: De-assert reset
[22] rstn_u1_plda_pcie_rstn_apb 1
  • 1: Assert reset
  • 0: De-assert reset
[31:23] Reserved 0 Reserved

STGCRG RESET Status

Table 31. STGCRG RESET Status Register Description
Offset 16’h78
Access RW
Bit Name Default Description
[0] rstn_u0_stg_syscon_presetn 0
  • 1: Assert reset
  • 0: De-assert reset
[1] rst_u0_hifi4_rst_core 1
  • 1: Assert reset
  • 0: De-assert reset
[2] rst_u0_hifi4_rst_axi 1
  • 1: Assert reset
  • 0: De-assert reset
[3] rstn_u0_sec_top_hresetn 1
  • 1: Assert reset
  • 0: De-assert reset
[4] rst_u0_e2_sft7110_rst_core 1
  • 1: Assert reset
  • 0: De-assert reset
[5] rstn_u0_dma1p_8ch_56hs_rstn_axi 1
  • 1: Assert reset
  • 0: De-assert reset
[6] rstn_u0_dma1p_8ch_56hs_rstn_ahb 1
  • 1: Assert reset
  • 0: De-assert reset
[7] rstn_u0_cdn_usb_rstn_axi 1
  • 1: Assert reset
  • 0: De-assert reset
[8] rstn_u0_cdn_usb_rstn_usb_apb 1
  • 1: Assert reset
  • 0: De-assert reset
[9] rstn_u0_cdn_usb_rstn_utmi_apb 1
  • 1: Assert reset
  • 0: De-assert reset
[10] rstn_u0_cdn_usb_rstn_pwrup 1
  • 1: Assert reset
  • 0: De-assert reset
[11] rstn_u0_plda_pcie_rstn_axi_mst0 1
  • 1: Assert reset
  • 0: De-assert reset
[12] rstn_u0_plda_pcie_rstn_axi_slv0 1
  • 1: Assert reset
  • 0: De-assert reset
[13] rstn_u0_plda_pcie_rstn_axi_slv 1
  • 1: Assert reset
  • 0: De-assert reset
[14] rstn_u0_plda_pcie_rstn_brg 1
  • 1: Assert reset
  • 0: De-assert reset
[15] rstn_u0_plda_pcie_rstn_pcie 1
  • 1: Assert reset
  • 0: De-assert reset
[16] rstn_u0_plda_pcie_rstn_apb 1
  • 1: Assert reset
  • 0: De-assert reset
[17] rstn_u1_plda_pcie_rstn_axi_mst0 1
  • 1: Assert reset
  • 0: De-assert reset
[18] rstn_u1_plda_pcie_rstn_axi_slv0 1
  • 1: Assert reset
  • 0: De-assert reset
[19] rstn_u1_plda_pcie_rstn_axi_slv 1
  • 1: Assert reset
  • 0: De-assert reset
[20] rstn_u1_plda_pcie_rstn_brg 1
  • 1: Assert reset
  • 0: De-assert reset
[21] rstn_u1_plda_pcie_rstn_pcie 1
  • 1: Assert reset
  • 0: De-assert reset
[22] rstn_u1_plda_pcie_rstn_apb 1
  • 1: Assert reset
  • 0: De-assert reset
[31:23] Reserved 0 Reserved