This topic documents the testing procedures and results for basic PLC function blocks
available in OpenPLC, including digital I/O, bistable elements, timers, counters, and
arithmetic operations.
Test Setup
The following table lists the hardware preparation and setup required for testing
OpenPLC function blocks on VisionFive 2 or VisionFive 2 Lite.
Table 1. Hardware Requirements
Item
Quantity
Purpose
VisionFive 2 / VisionFive 2 Lite
1
OpenPLC runtime platform
Breadboard
1
Circuit prototyping
LED
Several
Output indicators
Button/Switch
Several
Input signal sources
Resistor (100Ω)
Several
LED current limiting
L298N Motor Driver
1
DC motor speed control
DC Motor
1
Analog output load
Dupont Wires
Several
Circuit connections
USB2Serial Converter
1
Serial communication
Digital I/O and Analog Output Test
Verify that OpenPLC correctly reads digital inputs and writes digital and analog
outputs.
The OpenPLC hardware layer file for VisionFive 2 or VisionFive 2 Lite defines 14
digital outputs, 11 digital inputs, and 1 analog output. The figure below shows the
ladder diagram program and the address of each input/output point.
Note: The ladder diagram program is included in the downloaded
openplc.zip package: \openplc\6. Basic
functions.zip.
Test procedures:
Positive logic test:
Connect input I1 to a button (active high)
Connect output O1 to an LED
Configure O1 to mirror I1 state
Negative logic test:
Connect input I2 to a button (active high)
Connect output O2 to an LED
Configure O2 to invert I2 state
Series logic test:
Inputs I3 and I4 in series
Output O3 reflects combined result
Parallel logic test:
Inputs I5 and another input in parallel
Output O5 activates when either input is high
Analog output test:
Connect L298N PWM input to %QW0
Drive DC motor with variable speed control
Bistable (SR/RS) Test
Verify the operation of set dominant (SR) and reset dominant (RS) bistable function
blocks.
Test configuration:
Inputs I1 and I2 are connected to an RS bistable
Inputs I3 and I4 are connected to an SR bistable.
The output of the RS and SR bistable block goes to a rising edge detection
and a falling edge detection block respectively.
The rising edge detector is connected to the set input of the bistable RS0
and the falling edge detector is connected to the reset input of the
bistable RS1.
Figure 1. Bistable Test
In this test program, the output O1 is set if input I1 is active before inputs I2 and
I3. The output should remain set until I2 is triggered or I3-I4 is triggered in
sequence.
Timer (TON/TOF) Test
Verify the operation of timer-on-delay (TON) and timer-off-delay (TOF) function
blocks.
TON: Output Q activates after input IN is true for PT duration
TOF: Output Q deactivates after input IN goes false for PT
duration
For the segment of the ladder test program shown below, the output O2 is set to true
if one of the parallel TON timers receives an input pulse larger than the PT value.
Timers TON0 to TON3 are activated by the inputs I1, I2, I3, and I4. O2 should remain
active until the TOF timer in the series expires. For example, O2 is activated if I1
has been active for 1000 ms continuously, and it is automatically inactivated after
500 ms.Figure 2. Timer Test
Counter (CTU/CTD) Test
Verify the operation of count-up (CTU) and count-down (CTD) counter function
blocks.
CTU: A CTU counter increments the internal count variable CV on every
rising edge of the input CU. If the value in CV matches the user-defined PV
variable, the output Q is set to true. In the event of a rising edge in the
input R, the internal count variable CV is reset to zero.
CTD: CTD counter loads the internal CV variable value from PV on the
first rising edge of the input CD and decrements CV on every subsequent
rising edge of the input CD. Once CV reaches zero, the output Q is set to
true. Upon a rising edge on the input LD, the original PV value is restored
to CV.
The output O3 is set to true if CTU1 evaluates to true at least two times before a
reset pulse is received from CTD0. Inputs I1 and I2 are connected to the CU and R
inputs of the CTU0 counter, while inputs I3 and I4 are connected to the CD and LD
inputs of the CTD0 counter.Figure 3. Counter Test
Arithmetic and Comparison Test
Verify the operation of arithmetic and comparison function blocks.
Test configuration:
Connect a CTU counter to each of four inputs (I1, I2, I3, I4).
Wire the counter variables (CV) to arithmetic blocks.
