Display Controller Driver

• Host Interface: Allows communication with the system and the DC controller. The host interfaces include the AXI, AHB, and APB. In this block, data crosses clock domain boundaries.
• Memory Control: Contains the AXI interface to manage the access between the system memory and layers of the DC8200.
• Write Back: For debug use only.
• Layers: Include video/graphic, overlay, and cursor layers.
  • Video/graphic layers support both video and graphic configurations. Video/graphic and overlay layers support dynamic layer allocation and de-gamma.
  • Overlay 1 and overlay 3 do not support scaling, rotation, and line buffers.
  • Cursor layers provide hardware cursor functionality.
• Dither: Provides a Lookup Table (LUT).
• Gamma: Performs gamma correction.
• Output Panels: Support two output panels, as shown by Display0 and Display1.
• Output Interfaces: Support parallel pixel output with 30-bit Data, Horizontal Sync, Vertical Sync, and Data Enable. Support easy adaptation to external serialization logic, for example, HDMI.
• Pixel Pipelines: Reside in the layers and output panels. Two display pipelines support linear and tiled frame buffers for RGB and YUV inputs. Optional enhancements include multiple overlay layers, composition and blending, up/down scaling with multi-tap filtering, and color space conversions.

• Application layer: Consists of application code and test code and communicate with kernel layer through libdrm.
• Kernel layer: Consists of DRM core and Vout driver. DRM core receives commands from libdrm and transfers to Vout driver.
• Hardware layer: Connected with Vout driver, and operates the hardware directly.

display: display-subsystem {
        compatible = "startive,jh7110-display","verisilicon,display-subsystem";
        ports = <&dc_out_dpi0>;
        status = "disabled";
dssctrl: dssctrl@295B0000 {
        compatible = "starfive,jh7110-dssctrl","verisilicon,dss-ctrl", "syscon"; 
        reg = <0 0X295B0000 0 0x90>;
};

• compatible: Compatibility information, used to associate the display controller and its target device.
• ports: The port(s) used by the display controller.
• status: The work status of the display controller module. To enable the module, set this bit to okay. To disable the module, set this bit to disabled.
• reg: Register base address "0X295B0000" and range "0x90".

dc8200: dc8200@29400000 {
        compatible = "verisilicon,dc8200";
        verisilicon,dss-syscon = <&dssctrl>;
        reg = <0x0 0x29400000 0x0 0x100>,
              <0x0 0x29400800 0x0 0x2000>,
              <0x0 0x17030000 0x0 0x1000>;
        interrupts = <95>;
        status = "disabled";
        clocks = <&clkgen JH7110_NOC_BUS_CLK_CPU_AXI>,
                 <&clkgen JH7110_NOC_BUS_CLK_AXICFG0_AXI>,
                 <&clkgen JH7110_NOC_BUS_CLK_GPU_AXI>,
                 <&clkgen JH7110_NOC_BUS_CLK_VDEC_AXI>,
                 <&clkgen JH7110_NOC_BUS_CLK_VENC_AXI>,
                 <&clkgen JH7110_NOC_BUS_CLK_DISP_AXI>,
                 <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>,
                 <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>,
                 <&clkgen JH7110_VOUT_SRC>,
                 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
                 <&clkgen JH7110_AHB1>,
                 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>,
                 <&clkgen JH7110_VOUT_TOP_CLK_HDMITX0_MCLK>,
                 <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
                 <&clkvout JH7110_U0_DC8200_CLK_PIX0>,
                 <&clkvout JH7110_U0_DC8200_CLK_PIX1>,
                 <&clkvout JH7110_U0_DC8200_CLK_AXI>,
                 <&clkvout JH7110_U0_DC8200_CLK_CORE>,
                 <&clkvout JH7110_U0_DC8200_CLK_AHB>,
                 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AXI>,
                 <&clkvout JH7110_DOM_VOUT_TOP_LCD_CLK>,
                 <&hdmitx0_pixelclk>,
                 <&clkvout JH7110_DC8200_PIX0>,
                 <&clkvout JH7110_U0_DC8200_CLK_PIX0_OUT>,
                 <&clkvout JH7110_U0_DC8200_CLK_PIX1_OUT>;
        clock-names = "noc_cpu","noc_cfg0","noc_gpu","noc_vdec","noc_venc",
                      "noc_disp","noc_isp","noc_stg","vout_src",
                      "top_vout_axi","ahb1","top_vout_ahb",
                      "top_vout_hdmiTX0","i2stx","pix_clk","vout_pix1", 
                      "axi_clk","core_clk","vout_ahb",
                      "vout_top_axi","vout_top_lcd","hdmitx0_pixelclk","dc8200_pix0",
                      "dc8200_pix0_out","dc8200_pix1_out";
        resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>,
                 <&rstgen RSTN_U0_DC8200_AXI>,
                 <&rstgen RSTN_U0_DC8200_AHB>,
                 <&rstgen RSTN_U0_DC8200_CORE>,
                 <&rstgen RSTN_U0_NOC_BUS_CPU_AXI_N>,
                 <&rstgen RSTN_U0_NOC_BUS_AXICFG0_AXI_N>,
                 <&rstgen RSTN_U0_NOC_BUS_APB_BUS_N>,
                 <&rstgen RSTN_U0_NOC_BUS_DISP_AXI_N>,
                 <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>;
        reset-names = "rst_vout_src","rst_axi","rst_ahb","rst_core",
                      "rst_noc_cpu","rst_noc_axicfg0","rst_noc_apb",
                      "rst_noc_disp","rst_noc_stg";
        power-domains = <&pwrc JH7110_PD_VOUT>;
};

• compatible: Compatibility information, used to associate the display controller and its target device.
• dss-syscon: The SYSCON register(s) of the display panel.
• reg: Register base address "0x29400000" and range "0x100".
• interrupts: Hardware interrupt ID.
• status: The work status of the display controller module. To enable the module, set this bit to okay or to disable the module, set this bit to disabled.
• clocks: The clocks used by the display controller module.
• clock-names: The names of the above clocks.
• resets: The reset signals used by the display controller module.
• reset-names: The names of the above reset signals.
• power-domains: The power supply domain of the display controller module.