I2S Driver

The JH-7110 SoC Platform supports the following features and specifications on the audio codec interface.

  • Support playback
  • Support record
  • Support master/slave operation modes
  • Support multiple sample rate (with range 8 KHz - 48 KHz) for playback and record
  • Support 16-bit/32-bit sample width
  • Support up to 8 channels for both playback and record

Block Diagram

The following figure shows the block diagram of the audio codec interface.
Figure 1. Block Diagram

I2S Driver Device Tree Source Code

The following code block shows the device tree source code of the I2S driver.
   i2stx: i2stx@100c0000 {
compatible = "snps,designware-i2stx";
reg = <0x0 0x100c0000 0x0 0x1000>;
       interrupt-names = "tx";
       #sound-dai-cells = <0>;
       dmas = <&dma 28 1>;
       dma-names = "rx";
       status = "disabled";
};

i2srx_3ch: i2srx_3ch@100e0000 {
compatible = "snps,designware-i2srx";
       reg = <0x0 0x100e0000 0x0 0x1000>;
       clocks = <&clkgen JH7110_APB0>,
                <&clkgen JH7110_I2SRX0_3CH_CLK_APB>,
                <&clkgen JH7110_AUDIO_ROOT>,
                <&clkgen JH7110_MCLK_INNER>,
                <&clkgen JH7110_I2SRX_3CH_BCLK_MST>,
                <&clkgen JH7110_I2SRX_3CH_LRCK_MST>,
                <&clkgen JH7110_I2SRX0_3CH_BCLK>,
                <&clkgen JH7110_I2SRX0_3CH_LRCK>,
                <&clkgen JH7110_MCLK>,
                <&i2srx_bclk_ext>,
                <&i2srx_lrck_ext>;
       clock-names = "apb0", "3ch-apb",
                     "audioroot", "mclk-inner",
                     "bclk_mst", "3ch-lrck",
                     "rx-bclk", "rx-lrck",
                     "mclk", "bclk-ext",
                     "lrck-ext";
       resets = <&rstgen RSTN_U0_I2SRX_3CH_APB>,
                <&rstgen RSTN_U0_I2SRX_3CH_BCLK>;
       dmas = <&dma 24 1>;
       dma-names = "rx";
       starfive,sys-syscon = <&sys_syscon 0x18 0x34>;
       #sound-dai-cells = <0>;
       status = "disabled";
};

i2stx_4ch0: i2stx_4ch0@120b0000 {
       compatible = "snps,designware-i2stx-4ch0";
       reg = <0x0 0x120b0000 0x0 0x1000>;
       clocks = <&clkgen JH7110_MCLK_INNER>,
                <&clkgen JH7110_I2STX_4CH0_BCLK_MST>,
                <&clkgen JH7110_I2STX_4CH0_LRCK_MST>,
                <&clkgen JH7110_MCLK>,
                <&clkgen JH7110_I2STX0_4CHBCLK>,
                <&clkgen JH7110_I2STX0_4CHLRCK>;
       clock-names = "inner", "bclk-mst",
                     "lrck-mst", "mclk",
                     "bclk0", "lrck0";
       resets = <&rstgen RSTN_U0_I2STX_4CH_APB>,
                <&rstgen RSTN_U0_I2STX_4CH_BCLK>;
       dmas = <&dma 47 1>;
       dma-names = "tx";
       #sound-dai-cells = <0>;
       status = "disabled";
};

i2stx_4ch1: i2stx_4ch1@120c0000 {
compatible = "snps,designware-i2stx-4ch1";
       reg = <0x0 0x120c0000 0x0 0x1000>;
       clocks = <&clkgen JH7110_AUDIO_ROOT>,
                <&clkgen JH7110_MCLK_INNER>,
                <&clkgen JH7110_I2STX_4CH1_BCLK_MST>,
                <&clkgen JH7110_I2STX_4CH1_LRCK_MST>,
                <&clkgen JH7110_MCLK>,
                <&clkgen JH7110_I2STX1_4CHBCLK>,
                <&clkgen JH7110_I2STX1_4CHLRCK>,
                <&clkgen JH7110_MCLK_OUT>,
                <&clkgen JH7110_APB0>,
                <&clkgen JH7110_I2STX1_4CHCLK_APB>,
                <&mclk_ext>,
                <&i2stx_bclk_ext>,
                <&i2stx_lrck_ext>;
       clock-names = "audroot", "mclk_inner", "bclk_mst",
                     "lrck_mst", "mclk", "4chbclk",
                     "4chlrck", "mclk_out",
                     "apb0", "clk_apb",
                     "mclk_ext", "bclk_ext", "lrck_ext";
       resets = <&rstgen RSTN_U1_I2STX_4CH_APB>,
                <&rstgen RSTN_U1_I2STX_4CH_BCLK>;
       dmas = <&dma 48 1>;
       dma-names = "tx";
       #sound-dai-cells = <0>;
       status = "disabled";
};
The device tree code defines the following I2S audio controllers:
  • i2stx: 2S Transmit (audio output) controller
  • i2srx_3ch: I2S Receive (audio input) controller
  • i2stx_4ch0: I2S Transmit (4-channel audio output) controller
  • i2stx_4ch1: Second 4-channel I2S Transmit controller
The following table describes the DT parameters:
Table 1. I2S DT Parameters
Parameter Description
compatible Compatibility information, used to associate the driver and its target device
reg Register base address and offset
clocks The clocks used by the I2S module. Usually this parameter is filled with the system clock source or the clock of the module.
resets The reset signals used by the I2S module
dmas The DMA channel used by the module. For example, in the code <&dma 48 1>, 48 indicates the channel number; 1 indicates burst length is 4.
dma-names The names of the DMA channels, including "rx" for the receiver channel and "tx" for the transceiver channel
status

The work status of the I2S module. To enable the module, set this bit to okay. To disable the module, set this bit to disabled.

Source Code Structure

The following code block displays the source code structure for the I2S.
/freelight-u-sdk/linux/sound/soc/dwc
│ ├─ dwc-i2s.c // I2S driver source file for JH7110
│ ├─ local.h  // I2S driver header file for JH7110
│ ├─ i2srx-master.c // The source file while I2S works as the master
│ ├─ i2srx-master.h // The header file while I2S works as the master
/freelight-u-sdk/linux/sound/soc/codecs
│ ├─ wm8960.c and wm8960.h // external codec (WM8960) driver
│ ├─ ac108.c, ac108.h, ac101.c, ac101_regs.h, ac10x.h  // external codec (AC108) driver